This invention relates to a control circuit for at least one clock electrode, constituting a capacitive load, of an integrated circuit, which control circuit comprises at least two controllable semiconductor switches each having an output coupled to a terminal of the clock electrode, an input coupled to an associated terminal for connection to an associated direct voltage and a control input coupled to an associated terminal for coupling to a clock pulse generator so that the clock electrode is periodically switchable between two direct voltages.
A control circuit of this type for an integrated circuit, more particularly implemented as an image sensor, is known from an article in Philips Technical Review, Vol. 43, no. 1/2, December 1986, pp. 1 to 8, entitled "The accordion imager, a new solid-state image sensor". The two semiconductor switches are in the form of MOS transistors in which the output is a drain electrode, the input is a source electrode and the control input is a gate electrode. A first MOS transistor is of the p-channel type and a second is of the n-channel type and they are arranged in series between a terminal conveying a higher direct voltage and a terminal conveying a lower direct voltage. The gate electrodes are interconnected and are connected to the drain electrode of a third MOS transistor whose gate electrode is connected to the clock pulse generator. The three transistors jointly constitute an element of a shift register in which the gate electrode of the third transistor is connected to the drain electrodes of the first and second transistors of the previous shift register element. The described shift register implementation to the control circuit is specific of the so-called accordion control of the image sensor.
Apart from the specific implementation of the control circuit described, it appears that the clock electrode is periodically switched between the higher direct voltage and the lower direct voltage. The clock electrode then has a capacitance which is periodically charged and discharged via a series resistor. The series resistor not only comprises the source drain resistor of the conducting transistor but also parasitic series resistors. Recharging of the clock electrode capacitance is thereby accompanied by dissipative losses. These losses are dependent on many factors, particularly on the clock pulse frequency, the number of clock pulse phases, the values of the capacitances provided and the voltage difference between the higher and the lower voltage. The energy dissipation is not only unwanted because of its energy loss, but also because of the heating of the integrated circuit.